The ARC® Video Subsystem Family
The new family comprises five new subsystems that are based upon the VRaptor Multicore Architecture. Features and configuration for all five are shown in the table below:
Product Feature Configuration Decode Encode
AV 417V High Quality ARC 700 + Up to D1 Up to D1
Encode/Decode 2x SIMD MP
+ EE + ED + ME
AV 407V Reduced Die Size ARC 700 + Up to D1 Up to D1
Encode/Decode 1x SIMD MP
+ EE + ED + ME
AV 406V Low Power Encode ARC 700 + Up to CIF Up to D1
with Decode 1x SIMD MP
+ EE + ME
AV 404V Low Power Decode ARC 700 + Up to D1 Up to CIF
with Encode 1x SIMD MP
+ ED +EE
AV 402V Smallest Die Size ARC 700 + Up to CIF Up to CIF
Encode/Decode 1x SIMD MP
+ EE
Legend: SMID MP: Single Instruction, Multiple Data Media Processor CIF: Common Intermediate Format 384x288 at 30FPS
D1 Resolution: 720x576 (TV PAL) or 720x480 (TV NTSC)
EE: Entropy Encoder; ED: Entropy Decoder; ME: Motion Estimator
"ARC's new family of VRaptor-based video subsystems represent several steps forward for designers looking to use third Party IP to craft their next silicon solution," said Richard Wawrzyniak, senior market analyst for ASIC and SoC, at Semico Research Corp. "The subsystems' very low power consumption coupled with high performance and very small die size make them ideal to incorporate into next generation SoCs that are trying to hit low price points. In addition, the RISC processor in these heterogeneous, multicore subsystems can function as the processing element in many applications without needing to interface to a host processor making them even more attractive. They can double as processors themselves performing computing functions other than just those specific to the target feature set."
High Quality Video Encode - the New Frontier in Multimedia Processing
Websites such as YouTube that enable individuals to post personally crafted video vignettes are a social phenomenon rapidly spreading around the globe. However, video quality of this content suffers from being captured by low-quality encoders that are typical in today's camera phones and digital cameras.
With the high quality encode capability in the new ARC Video Subsystems, SoC developers can design chips that are differentiated and solve the disparate challenge of providing superior resolution encoding while consuming little power. Market opportunities for such products are booming. Research firms project the worldwide installed base of just camera phones will top 1.5 billion units by 2010, becoming the most prevalent image capture devices in the world.
ARC - Setting the Standard in Video Quality
The top of the new line of ARC Video Subsystems is the AV 417V. Using the City video benchmark (a 30-second video clip of the Manhattan skyline) it achieves approximately a 300 percent improvement in quality compared to quality from the encoders typically found in today's portable devices.
The ARC Video Subsystems achieve high quality video encode by employing algorithms ("tools") specified from standards bodies for video codecs such as H.264, which is up to five times more complex than other coding standards. Their high performance architecture (based on VRaptor) allows usage of the demanding encoding algorithms at reasonable clocking frequency resulting in a power-efficient solution.
The AV 417V Subsystem occupies just 4.95 mm2 in a 90nm process technology and achieves the following encode and decode performances:
· A H.264 BP encode of D1, 30 fps video stream of up to 10 Mbps bit rate, operating
under 200 MHz
· H.264 decode of D1, 30 fps video stream of 1.5Mbps bit rate, operating at 160 MHz
Low Power Via ARC's New "Dynamic Adaptive Encoding" Technology
A major innovation embodied in the new members of ARC's Video Subsystem Family is the patent pending technology called Dynamic Adaptive Encoding. The technology encodes video optimally under any system condition. Video encoding is a repetitive task that executes a set of algorithms to encode a digitized video stream or a set of digitized still images into such standards as H.264 BP, MPEG-4 SP/ASP, H.263 profile 0, and JPEG. Dynamic Adaptive Encoding continuously evaluates system resources and adaptively applies different processing resources to achieve the optimum result. For example, dynamic adaptive encoding allows the designer to adjust the encoding process in a phone with a fully charged battery versus one running close to empty.
ARC Video Subsystems - A New Way to Differentiate SoCs
Un-optimized, general purpose CPUs and DSPs cannot efficiently process complicated multimedia algorithms. Therefore, SoC designers typically have to implement numerous general purpose cores on a chip resulting in exploding silicon footprints and high power consumption. This approach is less than ideal for portable applications.
Alternatively, dedicated fixed-function hardware blocks are used to process specific media algorithms. However, this approach offers no programmability to adapt to evolving codec standards thereby limiting the product's life span.
ARC's Video Subsystems are uniquely optimized to the special processing needs of video and audio applications. They are as follows:
· Programmable to handle multi-format codecs and additional user-specific
applications
· Configurable to enable maximum product differentiation
· Pre-integrated and pre-verified to eliminate much of the software and hardware
design effort
· Efficient video encode using very low power and little silicon real estate
ARC VRaptor™ Multicore Architecture
The new members of the ARC Video Subsystem family are based upon the recently introduced VRaptor Multicore Architecture. It is a scalable heterogeneous processor architecture that overcomes the performance challenge of low power multimedia processing. VRaptor provides three distinct classes of ARC core modules. The first class includes a configurable 700 family core, and a range of specialized SIMD multimedia processors optimized for functions such as low-pass deblocking filters and pixel transforms. The second class includes accelerators, such as entropy encoders and decoders and motion estimators. These perform multimedia processing tasks more efficiently than general-purpose, programmable cores. And the third class includes high speed DMA controllers to relieve the CPU from complex data movement often found in multimedia codecs.
Connecting VRaptor's heterogeneous multicore resources together is its unique remote procedure invocation over communication channels capability. The 700 processor core, SIMD accelerators, DMA engine, entropy encoders and decoders, and motion estimation accelerators are all loosely coupled and operate independently of one another. The 700 processor core apportions work to each of the accelerators using a simple fire-and-forget message. The message in main memory enables a zero overhead context switch that directs the accelerator to perform a task and inform the 700 processor when complete, at which time the 700 processor immediately issues the accelerator another context switch that initiates another task. In this manner all the accelerators are kept running independently at full speed without having to await the result of any other processing resource in the system.
Jonah McLeod
ARC International
+1 408 437 3477
Jonah.McLeod@arc.com
Availability
The ARC Video Subsystem family is now available for licensing by companies worldwide. For more information contact ARC International at info@arc.com
or visit www.arc.com.
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